Modelling of Crosstalk and Delay for Distributed RLCG On-Chip Interconnects For Ramp Input

-In order to accurately model high frequency affects, inductance has been taken into consideration. No longer can interconnects be treated as mere delays or lumped RC networks. In that frequency range, the most accurate simulation model for on-chip VLSI interconnects is the distributed RLC model. Unfortunately, this model has many limitations at much higher of operating frequency used in today’s VLSI design. The reduction in cross-sectional dimension leads to more tightly couple interconnects and therefore, a higher probability of unwanted crosstalk interference. This can lead to inaccurate simulations if not modelled properly. At even higher frequency, the aggressor net carries a signal that couples to the victim net through the parasitic capacitances. To determine the effects that this crosstalk will have on circuit operation, the resulting delays and logic levels for the victim nets must be computed. This paper proposes a difference model approach to derive crosstalk and delay in the transform domain. A closed form solution for crosstalk and delay is obtained by incorporating initial conditions using difference model approach for distributed RLCG interconnects. The simulation is performed in 0.18μm technology node and an error of less than 1% has been achieved with the proposed model when compared with SPICE. Keywords-Crosstalk Model, Distributed RLCG Segment, Interconnect, Noise, Delay, VLSI